Efficient test compaction for combinational circuits based on Fault detection count-directed clustering

نویسندگان

  • Aiman H. El-Maleh
  • S. Saqib Khursheed
چکیده

Test compaction is an effective technique for reducing test data volume and test application time. In this paper, we present a new static test compaction algorithm based on test vector decomposition and clustering. Test vectors are decomposed and clustered in an increasing order of faults detection count. This clustering order gives more degree of freedom and results in better compaction. Experimental results demonstrate the effectiveness of the proposed approach in achieving higher compaction in a much more efficient CPU time than previous clustering-based test compaction approaches.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

A static test compaction technique for combinational circuits based on independent fault clustering

Testing system-on-chip involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the circuit under test during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount of test data in order to reduce both the total testing time and the memory requirements for the tester. In this ...

متن کامل

An Efficient Test Relaxation Technique for Combinational Circuits Based on Critical Path Tracing

Reducing test data size is one of the major challenges in testing systems-on-a-chip. This can be achieved by test compaction and/or compression techniques. Having a partially specified or relaxed test set increases the effectiveness of compaction and compression techniques. In this paper, we propose a novel and efficient test relaxation technique for combinational circuits. It is based on criti...

متن کامل

An Efficient Test Relaxation Technique for Combinational Logic Circuits

Reducing test data size is one of the major challenges in testing systems-on-a-chip. This can be achieved by test compaction and/or compression techniques. Having a partially specified or relaxed test set increases the effectiveness of compaction and compression techniques. In this paper, we propose a novel and efficient test relaxation technique for combinational circuits. It is based on criti...

متن کامل

Test set compaction for combinational circuits

Test set compaction for combinational circuits is studied in this paper. Two active compaction methods based on essential faults are developed to reduce a given test set. The special feature is that the given test set will be adaptly renewed to increase the chance of compaction. In the first method, forced pair-merging, pairs of patterns are merged by modifying their incompatible specified bits...

متن کامل

Proceedings of the International Test Conference , October 1998 Compact Two - Pattern Test Set Generation for Combinational and FullScan Circuits

This paper presents two algorithms for generating compact test sets for combinational and full scan circuits under the transition and CMOS stuck-open fault models; Redundant Vector Elimination (RVE) and Essential Fault Reduction (EFR). These algorithms together with the dynamic compaction algorithm are incorporated into an advanced ATPG system for combin-ational circuits, called MinTest. The te...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:
  • IET Computers & Digital Techniques

دوره 1  شماره 

صفحات  -

تاریخ انتشار 2007